1. Field of the Invention
The present invention generally relates to computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer. Certain embodiments relate to selecting a model for predicting printability of reticle features on a wafer by comparing one or more characteristics of reticle features of simulated images generated using different models for a set of different values of exposure conditions and one or more characteristics of reticle features printed on the wafer.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.
Lithography is typically one of the most important processes in integrated circuit (IC) manufacturing since a pattern printed in a resist by lithography is utilized as a masking layer to transfer the pattern to additional layers on a wafer in subsequent processing steps. Therefore, the pattern that is formed on the wafer during lithography directly affects the features of the ICs that are formed on the wafer. Consequently, defects that are formed on a wafer during lithography may be particularly problematic for the IC manufacturing process. One of the many ways in which defects may be formed on the patterned wafer during lithography is by transfer of defects that are present on the reticle to the wafer. Therefore, detection and correction of defects on the reticle such as unwanted particulate or other matter is performed rather stringently to prevent as many defects on the reticle from being transferred to the wafer during lithography.
However, as the dimensions of ICs decrease and the patterns being transferred from the reticle to the wafer become more complex, marginalities in the features formed on the reticle become increasingly important. Therefore, significant efforts have been devoted to developing methods and systems that can be used to detect problems in the pattern on the reticle or in the design that will cause problems on the wafer. These efforts are relatively complex and difficult due, at least in part, to the fact that not all discrepancies or marginalities in the pattern formed on the reticle will cause errors on the wafer that will adversely affect the IC. In other words, some marginalities in the pattern formed on the reticle may not produce defects on the wafer at all or may produce defects on the wafer that will not reduce the performance characteristics of the IC. Therefore, one challenge of many in developing adequate methods and systems for qualifying a reticle pattern is to discriminate between pattern defects or marginalities that “matter” and those that do not.
One way to check a reticle pattern before the reticle is fabricated is design rule checking (DRC). However, conventional DRC operates only at the nominal process conditions or, at most, at a limited number of process conditions and/or at a limited number of points within the device. Other software-based methods for detecting design pattern defects prior to fabrication of the reticle have been proposed, and one such method is described in U.S. Patent Application Publication No. 2003/0119216A1 by Weed, which is incorporated by reference as if fully set forth herein. However, this method is designed to determine only the best focus and exposure settings and not to explore the full range of the process window conditions available for each design.
Such software methods, therefore, have several disadvantages. In particular, these software methods do not examine the full range of process window conditions thereby failing to detect process window marginalities and missing potential defects. In addition, these methods do not determine the exact focus and exposure conditions under which defects will occur thereby preventing the complete optimization of the design. The lack of complete process window information also limits the ability to implement advanced process control techniques for critical dimension control across all critical features on the device.
If the layout of a reticle design passes verification, reticle enhancement technique (RET) features may be added to the circuit layout. This step is commonly referred to as “decorating” the circuit layout. Adding the RET features to the circuit layout may be performed in a number of different ways. The RET features may include a number of different RET features such as optical proximity correction (OPC) features. The decoration may also be verified prior to reticle fabrication. Verifying the decoration may include optical rule checking (ORC). If the decorated design fails verification, the RET features in the decorated design may be altered, and the decorated design may be re-verified.
Currently, many methods for calibrating OPC feature models and OPC feature verification models involve generating a number of models and choosing the one that best simulates the wafer data. The calibration is typically performed based on data at a single focus and exposure condition or on data at focus and exposure conditions concentrated near the best focus and exposure condition. This approach has the disadvantage that the simulations may not be accurate across the entire process window and at other arbitrary focus and exposure conditions. In addition, the data is typically collected and interpreted manually in the currently used methods, which increases the probability of error in the calibration.
Accordingly, it would be desirable to develop computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer for a set of different values of exposure conditions automatically.